MRF89XA-I/MQ【PDF 88/140 页】TXRX ISM SUB-GHZ ULP 32QFN

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MRF89XA

3.11.6

HOST MICROCONTROLLER

FIGURE 3-32:

HOST MCU

INTERFACE CONNECTIONS IN

PACKET MODE

Depending on the application, some of the host

microcontroller connections may not be needed:

? IRQ0: If none of the relevant IRQ sources are

used. In this case, leave the pin floating.

MRF89XA

CONNECTIONS IN

PACKET MODE

IRQ0

IRQ1

? IRQ1: If none of the relevant IRQ sources are

used. In this case, leave the pin floating.

? SDO: If no read register access is needed and the

device is used in TX mode only. In this case, pull

up to V DD through a 100 k ? resistor.

The DATA pin (pin 20), which is unused in

Note:

Packet mode, should be pulled-up to V DD

through a 100 k ? resistor. Table 2-4 , pro-

C SCON

CSDAT

SCK

SDI

SDO

PIC ?

Microcontroller

vides details about MRF89XA pin configu-

ration and chip mode.

3.11.7 PACKET MODE EXAMPLE

The data processing related registers are appropriately

configured as shown in Table 3-13 . In this example we

assume CRC is enabled with autoclear on.

TABLE 3-13:

CONFIGURATION REGISTERS RELATED TO DATA PROCESSING (ONLY) IN

PACKET MODE

Register Name

DMODREG

FIFOCREG

FIFOCREG

FTXRXIREG

FTXRXIREG

FTXRXIREG

FTPRIREG

SYNCREG

SYNCREG

SYNCREG

SYNCV31REG

SYNCV23REG

SYNCV15REG

SYNCV07REG

PLOADREG

PLOADREG

NADDSREG

PKTCREG

PKTCREG

PKTCREG

PKTCREG

PKTCREG

PKTCREG

FCRCERG

FCRCERG

Register Bits

DMODE0, DMODE1

FSIZE<1:0>

FTINT<5:0>

IRQ0RXS<1:0>

IRQ1RXS<1:0>

IRQ1TX

IRQ0TXST

SYNCREN

SYNCWSZ<1:0>

SYNCTEN<1:0>

SYNCV<31:24>

SYNCV<23:16>

SYNCV<15:8>

SYNCV<7:0>

MCHSTREN

PLDPLEN<6:0>

NLADDR<7:0>

PKTLENF

PRESIZE<1:0>

WHITEON

CRCEN

ADDFIL<1:0>

CRCSTSEN

ACFCRC

FRWAXS

TX

X

X

X

—

—

X

X

—

—

—

—

—

—

—

X

X (1)

—

X

X

X

X

—

X

—

X

RX

X

X

X

X

X

—

—

X

X

X

X

X

X

X

X

X

X

X

—

X

X

X

X

X

X

Description

Defines data operation mode ( Packet)

Defines FIFO size

Defines FIFO threshold

Defines IRQ0 source in RX & Stand-by modes

Defines IRQ1 source in RX & Stand-by modes

Defines IRQ1 source in TX mode

Defines IRQ0 source in TX mode

Enables Sync word recognition

Defines Sync word size

Defines the error tolerance on Sync word recognition

Defines Sync word value

Defines Sync word value

Defines Sync word value

Defines Sync word value

Enables Manchester encoding/decoding

Length in fixed format, max RX length in variable format

Defines node address for RX address filtering

Defines packet format (fixed or variable length)

Defines the size of preamble to be transmitted

Enables whitening/de-whitening process

Enables CRC calculation/check

Enables and defines address filtering

Enables CRC Status check

Enables FIFO autoclear if CRC failed

Defines FIFO access in Stand-by mode

Note 1:

Fixed format only.

DS70622C-page 88

Preliminary

? 2010–2011 Microchip Technology Inc.

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